The present invention relates to reconfigurable chips. Reconfigurable chips are chips that can be configured to a number of different uses. A reconfigurable chip that recently has been found to be quite useful is a reconfigurable chip used to implement an algorithm, such as a communications system algorithm. Sections of the algorithm are swapped in and out of the reconfigurable chip as needed.
FIG. 1 shows a prior-art floorplan for such a reconfigurable chip. In floorplan 40 is shown an ASIC portion 42 which implements a central processor unit and other logic needed for the reconfigurable chip. Also shown is a reconfigurable fabric section 44 which implements the reconfigurable logic of the system. In one embodiment, the fabric 44 is divided into slices such as slice 46. Each of the slices is composed of a number of tiles 48. Each of the tiles contains a number of reconfigurable functional units, or data path units. These reconfigurable functional units preferably use a dedicated arithmetic logic unit (ALU). Preferably, the elements within a region such as slices and tiles are more interconnected than elements in different regions.
A disadvantage with the division of slices as shown in FIG. 1 is that the reconfigurable fabric portion 44 tends to be longer than it is wide. These long interconnections make it difficult to meet timing requirements, especially for connections between the ASIC portion 42 and the portions on the far side of a slice. The resistive/capacitive (RC) constant for these interconnection regions tends to be relatively high, producing a longer flight time with relatively slow rise and fall times resulting in a relatively high power dissipation.
It is desired to have an improved floorplan that improves on the timing for interconnection of elements on a reconfigurable chip.
One embodiment of the present invention comprises a region on the reconfigurable chip including four slices, each of the slices being adjacent to a corner of the region. Each slice has multiple tiles; each tile has multiple reconfigurable logic units; and each reconfigurable logic unit includes an arithmetic logic unit.
By placing the slices adjacent to each corner of the region on the reconfigurable chip, the interconnection time between the reconfigurable logic units on the chip is reduced. Additionally, the regions with slices in the four corners have an aspect ratio closer to one than when elongated slices are used.
In one embodiment, the slices are rectangular. In another embodiment the slices are L-shaped to allow a center logic portion within the region. The regions described above have the advantage in that they can be placed within an even greater sized region of the floorplan. Four such regions can be put in the corners of an even greater region on the chip. The regions of the present invention are thus much more scalable for additional designs.
Another embodiment of the present invention uses a multiplexer receiving inputs from at least three reconfigurable logic units. The multiplexer is operably connected to an interconnect bus. Such an interconnection system using such multiplexer helps remove the tri-state buffers from the bus system and thus reduces the RC constant for this system and reduces the interconnection times. This multiplexer system has a slight downside in that it reduces some of the interconnection flexibility. However, in many cases, the interconnection speed benefit outweighs this disadvantage.